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Ocs package (edit)

Revision as of 06:36, 22 September 2015

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→‎Build the AND gate circuit structure parsing an IFF netlist
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==== Build the AND gate circuit structure parsing an IFF netlist ====
==== Build the AND gate circuit structure parsing an IFF netlist ====
To parse an IFF format netlist of the CMOS AND gate we can use the following command


{{Code|Load the AND circuit structure parsing an IFF netlist |<syntaxhighlight lang="octave" style="font-size:13px">
{{Code|Load the AND circuit structure parsing an IFF netlist |<syntaxhighlight lang="octave" style="font-size:13px">
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</syntaxhighlight>
</syntaxhighlight>
}}
}}
The IFF netlist consists of the .cir file named "and.cir" shown below


{{Code|IFF netlist for the AND gate (.cir file)|<syntaxhighlight lang="text" style="font-size:13px">
{{Code|IFF netlist for the AND gate (.cir file)|<syntaxhighlight lang="text" style="font-size:13px">
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</syntaxhighlight>
</syntaxhighlight>
}}
}}
and of the .nms file named "and.nms shown below


{{Code|IFF netlist for the AND gate (.nms file)|<syntaxhighlight lang="text" style="font-size:13px">
{{Code|IFF netlist for the AND gate (.nms file)|<syntaxhighlight lang="text" style="font-size:13px">
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</syntaxhighlight>
</syntaxhighlight>
}}
}}
{{Code|Model evaluator file for simple MOSFET models |<syntaxhighlight lang="octave" style="font-size:13px">
function [a,b,c] = Mnmosfet (string, parameters, parameternames, extvar, intvar, t) 
 
  switch string
    case 'simple',
     
      rd = 1e6;
     
      for ii=1:length(parameternames)
        eval([parameternames{ii} "=",...
              num2str(parameters(ii)) " ;"])   
      endfor
     
      vg  = extvar(1);
      vs  = extvar(2);
      vd  = extvar(3);
      vb  = extvar(4);
     
      vgs  = vg-vs;
      vds  = vd-vs;
     
      if (vgs < Vth)
       
       
        gm = 0;
        gd = 1/rd;
        id = vds*gd;
       
      elseif ((vgs-Vth)>=(vds))&(vds>=0)
       
        id = k*((vgs-Vth)*vds-(vds^2)/2)+vds/rd;
        gm = k*vds;
        gd = k*(vgs-Vth-vds)+1/rd;
       
      elseif ((vgs-Vth)>=(vds))&(vds<0)
       
        gm = 0;
        gd = 1/rd;
        id = vds*gd;
       
      else # (i.e. if 0 <= vgs-vth <= vds)
       
        id = k*(vgs-Vth)^2/2+vds/rd;
        gm = k*(vgs-Vth);
        gd = 1/rd;
       
      endif
     
      a = zeros(4);
     
      b = [ 0    0        0  0;
          -gm  (gm+gd)  -gd  0;
            gm  -(gm+gd)    gd  0;
            0    0        0  0];
     
      c = [0 -id id 0]';
      break;
    otherwise
      error(["Mnmosfet: unknown option " string]);
     
  endswitch
endfunction
</syntaxhighlight>
}}


==== Build the AND gate circuit structure parsing a .spc file ====
==== Build the AND gate circuit structure parsing a .spc file ====
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