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Ocs package: Difference between revisions
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→Build the AND GATE structure directly
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## NLC | |||
# n-type | |||
outstruct.NLC(1).func = "Mnmosfet"; | |||
outstruct.NLC(1).section = "simple"; | |||
outstruct.NLC(1).nextvar = 4; | |||
outstruct.NLC(1).npar = 3; | |||
outstruct.NLC(1).nparnames = 3; | |||
outstruct.NLC(1).parnames = { "k", "Vth", "rd"}; | |||
outstruct.NLC(1).pvmatrix = [1.0000e-04 1.0000e-01 1.0000e+07 | |||
1.0000e-04 1.0000e-01 1.0000e+07 | |||
1.0000e-04 1.0000e-01 1.0000e+07]; | |||
outstruct.NLC(1).vnmatrix = [1 3 4 0 | |||
2 0 3 0 | |||
4 0 5 0]; | |||
outstruct.NLC(1).nintvar = [0 0 0]; | |||
outstruct.NLC(1).osintvar = [0 0 0]; | |||
# p-type | |||
outstruct.NLC(2).func = "Mpmosfet"; | |||
outstruct.NLC(2).section = "simple"; | |||
outstruct.NLC(2).nextvar = 4; | |||
outstruct.NLC(2).npar = 3; | |||
outstruct.NLC(2).nparnames = 3; | |||
outstruct.NLC(2).parnames = { "k", "Vth", "rd"}; | |||
outstruct.NLC(2).pvmatrix = [-1.0000e-04 -1.0000e-01 1.0000e+07 | |||
-1.0000e-04 -1.0000e-01 1.0000e+07 | |||
-1.0000e-04 -1.0000e-01 1.0000e+07]; | |||
outstruct.NLC(2).vnmatrix = [ 1 6 4 6 | |||
2 6 4 6 | |||
4 6 5 6]; | |||
outstruct.NLC(2).nintvar = [0 0 0]; | |||
outstruct.NLC(2).osintvar = [0 0 0]; | |||
# Va and Vb | |||
outstruct.NLC(3).func = "Mvoltagesources"; | |||
outstruct.NLC(3).section = "sinwave"; | |||
outstruct.NLC(3).nextvar = 2; | |||
outstruct.NLC(3).npar = 4; | |||
outstruct.NLC(3).nparnames = 4; | |||
outstruct.NLC(3).parnames = {"Ampl", "f", "delay", "shift"}; | |||
outstruct.NLC(3).pvmatrix = [0.50000 1.00000 0.00000 0.50000 | |||
0.50000 2.00000 0.25000 0.50000]; | |||
outstruct.NLC(3).vnmatrix = [ 1 0 | |||
2 0]; | |||
outstruct.NLC(3).nintvar = [1 1]; | |||
outstruct.NLC(3).osintvar = [0 0]; | |||
## LCR | |||
# Vdd | |||
outstruct.LCR(1).func = "Mvoltagesources"; | |||
outstruct.LCR(1).section = "DC"; | |||
outstruct.LCR(1).nextvar = 2; | |||
outstruct.LCR(1).npar = 1; | |||
outstruct.LCR(1).nparnames = 1; | |||
outstruct.LCR(1).parnames = {"V"}; | |||
outstruct.LCR(1).pvmatrix = 1; | |||
outstruct.LCR(1).vnmatrix = [6 0]; | |||
outstruct.LCR(1).nintvar = 1; | |||
outstruct.LCR(1).osintvar = 2; | |||
## | |||
outstruct.namesn = [1 2 5 6 7 8 9]; | |||
outstruct.namess = {"Va", "Vb", "Va_and_b", "Vdd", "I1", "I2", "I3"}; | |||
outstruct.totextvar = 6; | |||
outstruct.totintvar = 3; | |||
==== Build the AND gate circuit structure parsing an IFF netlist ==== | ==== Build the AND gate circuit structure parsing an IFF netlist ==== | ||