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Latest revision | Your text | ||
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__TOC__ | __TOC__ | ||
== History and Motivation == | == History and Motivation == | ||
== Problem Formulation == | == Problem Formulation == | ||
== Data Structure == | == Data Structure == | ||
== File Formats == | == File Formats == | ||
== Tutorials == | == Tutorials == | ||
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** 6 MOSFETs (3 n-type + 3 p-type) | ** 6 MOSFETs (3 n-type + 3 p-type) | ||
** 3 Voltage sources | ** 3 Voltage sources | ||
Below we show three methods for constructing the circuit data structure | Below we show three methods for constructing the circuit data structure | ||
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Once the circuit data structure is loaded the simulation can be started by the following commands | Once the circuit data structure is loaded the simulation can be started by the following commands | ||
[[File:AND_result.png|thumb| Result of the CMOS AND gate switching simulation]] | |||
{{Code|Run the AND gate simulation |<syntaxhighlight lang="octave" style="font-size:13px"> | {{Code|Run the AND gate simulation |<syntaxhighlight lang="octave" style="font-size:13px"> | ||
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</syntaxhighlight> | </syntaxhighlight> | ||
}} | }} | ||
Click on the figure to the right to see the simulation results | Click on the figure to the right to see the simulation results | ||
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==== Build the AND gate circuit structure parsing an IFF netlist ==== | ==== Build the AND gate circuit structure parsing an IFF netlist ==== | ||
{{Code|Load the AND circuit structure parsing an IFF netlist |<syntaxhighlight lang="octave" style="font-size:13px"> | {{Code|Load the AND circuit structure parsing an IFF netlist |<syntaxhighlight lang="octave" style="font-size:13px"> | ||
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</syntaxhighlight> | </syntaxhighlight> | ||
}} | }} | ||
{{Code|IFF netlist for the AND gate (.cir file)|<syntaxhighlight lang="text" style="font-size:13px"> | {{Code|IFF netlist for the AND gate (.cir file)|<syntaxhighlight lang="text" style="font-size:13px"> | ||
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</syntaxhighlight> | </syntaxhighlight> | ||
}} | }} | ||
{{Code|IFF netlist for the AND gate (.nms file)|<syntaxhighlight lang="text" style="font-size:13px"> | {{Code|IFF netlist for the AND gate (.nms file)|<syntaxhighlight lang="text" style="font-size:13px"> | ||
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}} | }} | ||
== | {{Code|Model evaluator file for simple MOSFET models |<syntaxhighlight lang="octave" style="font-size:13px"> | ||
function [a,b,c] = Mnmosfet (string, parameters, parameternames, extvar, intvar, t) | |||
switch string | |||
case 'simple', | |||
rd = 1e6; | |||
for ii=1:length(parameternames) | for ii=1:length(parameternames) | ||
eval([parameternames{ii} "=",... | |||
num2str(parameters(ii)) " ;"]) | |||
endfor | endfor | ||
vg = extvar(1); | |||
vs = extvar(2); | |||
vd = extvar(3); | |||
vb = extvar(4); | |||
vgs = vg-vs; | |||
vds = vd-vs; | |||
if (vgs < Vth) | |||
gm = 0; | |||
gd = 1/rd; | |||
id = vds*gd; | |||
elseif ((vgs-Vth)>=(vds))&(vds>=0) | |||
id = k*((vgs-Vth)*vds-(vds^2)/2)+vds/rd; | |||
gm = k*vds; | |||
gd = k*(vgs-Vth-vds)+1/rd; | |||
elseif ((vgs-Vth)>=(vds))&(vds<0) | |||
gm = 0; | |||
gd = 1/rd; | |||
id = vds*gd; | |||
else # (i.e. if 0 <= vgs-vth <= vds) | |||
id = k*(vgs-Vth)^2/2+vds/rd; | |||
gm = k*(vgs-Vth); | |||
gd = 1/rd; | |||
- | |||
< | |||
endif | endif | ||
a = zeros(4); | |||
b = [ 0 0 0 0; | |||
-gm (gm+gd) -gd 0; | |||
gm -(gm+gd) gd 0; | |||
0 0 0 0]; | |||
c = [0 -id id 0]'; | |||
break; | break; | ||
otherwise | |||
error(["Mnmosfet: unknown option " string]); | |||
endswitch | endswitch | ||
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==== Build the AND gate circuit structure parsing a .spc file ==== | |||
{{Code|Load the AND circuit structure parsing a .spc file |<syntaxhighlight lang="octave" style="font-size:13px"> | |||
outstruct = prs_spice ("and"); | |||
</syntaxhighlight> | |||
}} | |||
{{Code|Load the AND circuit structure parsing a .spc file |<syntaxhighlight lang="octave" style="font-size:13px"> | |||
outstruct = prs_spice ("and"); | |||
</syntaxhighlight> | </syntaxhighlight> | ||
}} | }} | ||