File:AND BW.png

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Circuit Schematic for a CMOS AND gate to be simulated in OCS

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	Date/Time	Thumbnail	Dimensions	User	Comment
current	05:37, 22 September 2015		1,031 × 742 (42 KB)	Cdf (talk \| contribs)	Circuit Schematic for a CMOS AND gate to be simulated in OCS

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